The present invention relates to a semiconductor device technique, and relates to a technique effective for applying, for example, a semiconductor device technique including a bump electrode.
For example, Japanese Unexamined Patent Application Publication No. 2009-302227 and Japanese Unexamined Patent Application Publication No. 2010-93109 describe a structure in which an electrode of a semiconductor chip mounted on a wiring substrate is extracted to the outside through a bump electrode arranged on a mounting surface of the wiring substrate.
Japanese Unexamined Patent Application Publication No. 2009-302227 discloses a land-on-via structure in which a via penetrating a wiring substrate is directly connected with a land where a bump electrode is formed, an NSMD (Non Solder Mask Defined) structure in which the land is included in an opening portion of a solder resist formed on a mounting surface of the wiring substrate, and an SMD (Solder Mask Defined) structure whose peripheral part is covered with the solder resist formed on the mounting surface of the wiring substrate.
Further, Japanese Unexamined Patent Application Publication No. 2010-93109 discloses a structure in which a group of solder balls arranged on the outer peripheral side of a mounting surface of a wiring substrate while being circulated in a plurality of rows and a group of solder balls arranged on the central side of the mounting surface of the wiring substrate while being circulated in a plurality of rows are provided on the mounting surface of the wiring substrate.